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br34l02fv - w memory ics rev.a 1/24 256 8 bit electrically erasable prom (based on serial presence detect) br34l02fv - w t h e br 34 l02 fv -w i s a 2 k bi t eepr om me mory w i th w r ite - p r ote c t fu n c tio n h a ving i nde pen de nt re w r i t e in hi bi t a r ea , d e v e l o p ed f o r a di mm t hat us es s y n c hr on o u s dram me mor y , a n d a rimm th at us es ram b us dr am m e m o r y . t h is is a memory ic that reads id in order for the plug & play feature to operate. ? i 2 c bus is a registered trademark of philip s. z a pplic a t ions general purpose z f eatu r es 1) 256k registers 8 bit s serial architecture 2) single pow er supply (1.8v to 5.5v) 3) t w o w i re serial interface 4) page w r ite f unction (16by te) 5) w r ite protect mode w r ite protect 1 (onetime rom) : 00h to 7f h w r ite protect 2 (hardw ire w p pin) : 00h to f f h 6) low pow e r consumption w r ite (5v) : 1.2ma (t y p .) read (5v) : 0.2ma (t y p .) s t andby (5v) : 0.1 a ( t y p . ) 7) da t a security w r ite protect feature (w p pin) inhibit to writ e at low v cc 8) small p a ckage - - - - - - ssop-b8 pin 9) high reliability fine p a ttern cmos technology 10) endurance : 1,000,000 erase/w r ite cy cles 1 1 ) dat a retention : 40y ears 12) f iltered input s in scl ? sda for noise suppression 13) initial dat a f f h in all address z a b solute maximum ratings (t a= 25 c) parameter symbol limits unit supply voltage ? 0.3 to + 6.5 v power dissipation mw storage temperature ? 65 to + 125 c operating temperature c terminal voltage ? v ? 40 to + 85 v cc ? 0.3 to v cc + 0.3 pd tstg topr ? 1 300(ssop-b8) ? 1 reduced by 3.0mw for each increase in ta of 1 c over 25 c.
br34l02fv - w memory ics rev.a 2/24 z re c o mme nde d ope ra ting c onditions (t a= 25 c) parameter symbol limits unit supply voltage v input voltage v in v v cc 0 to v cc 1.8 to 5.5 z dc o p e ratin g ch aracteristics (unless otherw i se specified t a = ? 40 to 85 c, v cc = 1.8 to 5.5v) parameter symbol min. typ. max. unit conditions v ih1 ?? v v il1 ?? 0.3 v cc v v ol2 ?? 0.2 v input leakage current 1 i li 1 ? + 1 a v in = 0v to v cc output leakage current i lo ? 1 input leakage current 2 i l i 2 ? + 15 a v in = 0v to v cc (wp) ? 1 ? 1 ? + 1 a operating current i cc2 ? 0.5 ma standby current i sb ? ? i cc1 ? 2.0 ma ? ? 2.0 a 0.7v cc 2.5v v cc 5.5v 2.5v v cc 5.5v i ol = 0.7ma, 1.8v v cc < 2.5v, (sda) v cc = 5.5v, f scl = 400khz random read, current read, sequential read v out = 0v to v cc "high" input volatge 1 "low" input volatge 1 v ih2 ?? v v il2 ?? 0.2 v cc v 0.8v cc 1.8v v cc <2.5v 1.8v v cc <2.5v "high" input volatge 2 "low" input volatge 2 v ol1 ?? 0.4 v i ol = 3.0ma, 2.5v v cc 5.5v, (sda) "low" output volatge 2 "low" output volatge 1 v cc = 5.5v, sda ? scl = v cc , a0, a1, a2=gnd, wp=gnd v cc = 5.5v, f scl = 400khz, t wr =5ms, byte write, page write, write protect ? this product is not designed for protection against radioactive rays. z dime ns ion 5 4 8 1 0.1 6.4 0.3 4.4 0.2 3.0 0.2 0.22 0.1 1.15 0.1 0.65 (0.52) 0.15 0.1 0.3min. 0.1 fig.1 physical dimension ssop-b8 (units : mm)
br34l02fv - w memory ics rev.a 3/24 z blo ck d i ag ram 1 a0 a1 2 a2 3 gnd 4 v cc 8 wp 7 6 scl sda 5 2kbit eeprom array control logic high voltage generator vcc level detect 8bit 8bit ack stop start address decoder slave word address register 8bit data register fig.2 block diagram z pin c onfigura t ion BR34L02FV-W v cc a0 wp a1 scl a2 sda gnd 123 4 5 6 7 8 fig.3 pin layout z pin d escrip tio n s write protect input power supply function ground (0v) slave address set serial clock input sda v cc a0, a1, a2 pin name gnd wp scl i / o ? ? in in in in / out slave and word address, serial data input, serial data output 1 an open drain output requires a pull-up resistor. 2 wp pin has a pull-down resistor. please be left unconnected or connect to gnd when wp feature is not in use. 1 2
br34l02fv - w memory ics rev.a 4/24 z t est circu i t v cc v cc sda gnd vol i ol v fig.4 "l" output voltage test circuit output="l" v cc v cc a0, a1, a2 sda, sci, wp gnd ili ilo a fig.5 input/output current test circuit vout = 0 to v cc vin = 0 to v cc v cc v cc v cc scl sda wp a0, a1, a2 gnd icc a fig.6 power consumption test circuit write/read input 400khz clock v cc v cc v cc scl sda wp a0, a1, a2 gnd isb a fig.7 standby current voltage test circuit
br34l02fv - w memory ics rev.a 5/24 z a c o p e ratin g ch aracteristics (unless otherw i se specified t a = ? 40 to 85 c, v cc = 1.8 to 5.5v) parameter fast-mode 2.5v vcc 5.5v standard-mode 1.8v vcc 5.5v unit khz noise spike width (sda and scl) ms data clock "high" period clock frequency s data clock "low" period s sda and scl rise time ? 1 ? 1 ? 1 not 100% tested. s sda and scl fall time s start condition hold time s start condition setup time s input data hold time ns input data setup time ns output data delay time output data hold time s stop condition setup time s bus free time s min. ? 0.6 ? ? 1.2 ? ? 0.6 0.6 0 50 0.1 0.1 0.6 1.2 typ. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? max. 400 ? 5 ? 0.3 0.3 ? ? ? ? 0.9 ? ? ? min. ? 4.0 ? ? 4.7 ? ? 4.0 4.7 0 50 0.2 0.2 4.7 4.7 typ. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? max. 100 ? wp high period s 0.1 ?? 0.1 ?? 5 0.1 ? 1.0 0.3 ? ? ? ? 3.5 wp setup time ns s 0 ? ? 0.1 0 ? ? ? ? ? s write cycle time wp hold time symbol fscl thigh twr tl tlow tr tf thd:sta tsu:sta thd:dat tsu:dat tpd tdh tsu:sto tbuf tsu:wp thd:wp thigh:wp s 1.0 ?? 1.0 ??
br34l02fv - w memory ics rev.a 6/24 z sy nc hronous da t a timing t buf t pd t high t hd : sta t low t f t r scl start bit stop bit scl sda t dh t su : dat t hd : dat t su : sto t hd : sta t su : sta sda (out) sda (in) fig.8 synchronous data timing ? sda dat a is latched into the chip at the rising edge of scl clock. ? output dat a toggles at t he falling edge of scl clock. z w r ite cy cle timin g ack d0 t wr sda scl start condition stop condition write data (n) fig.9 write cycle timing
br34l02fv - w memory ics rev.a 7/24 z wp timing scl sda wp t hd : wp t wr stop bit ack ack d1 data (n) data (1) t su : wp d0 fig.10(a) wp timing of the write operation scl sda wp ack ack d1 data (n) data (1) t high : wp d0 fig.10(b) wp timing of the write cancel operation ? f o r the w r it e operation, w p must be ?low ? during the period of time from the rising edge of the clock w h ich t a kes in d0 of first by te until the end of t wr . (see f i g.10(a) ) during this period, w r it e operation is c anceled by setting w p ?high?. (see f i g.10(b)) ? in the case of setting wp ?high? during t wr , w r it e operation is stopped in the middle and the dat a of accessing address is not guaranteed. please w r it e correct dat a again in the case.
br34l02fv - w memory ics rev.a 8/24 z de v i c e ope ra tion 1) s t art condition (recognition of st art bit) ? all commands are proceeded by the st art condition, w h ich is a high to low transition of sda w hen scl is high. ? t he device continuously monitors the sda and scl lines for the st art condition and w ill not respond to any command until this condition has been met. (see fig.8 synchronous da t a t i ming) 2) s t op condition (recognition of stop bit) ? all communications must be terminated by a stop condition, w h ich is a low to high transition of sda w hen scl is high. (see fig.8 synchronous da t a t i ming) 3) notice about w r ite command ? in the case that stop condition is not executed in w r it e mode, transferred dat a w ill not be w r itten in a memory . 4) device addressing ? f o llow i ng a st ar t condition, the master output the device address to be accessed. t he most significant four bit s of the slave address are the ? device ty pe identifier?. f o r the device this is fixed as ?1010?. (in access to w p resister , this code use ?01 10?.) ? t he next three bit (device address) address a p a rticular to the bus. t he device address is defined by the st art of a0, a1 and a2 input pins. t h is ic w o rks only w hen the device address inputted from sda pin correspond to the st ate of a0, a1 and a2 input pins. using this address scheme, up to eight device may be connected, to the bus. t he last bit of the stream (r/w - - - read/w rit e ) determines the operation to the performed. r/w = 0 w r it e (including w o rd address input of random read) r/w=1 read a2 a1 a0 access to memory access to write protect resister 1010 r / w a2 a1 a0 0110 r / w device type device address 5) w r ite protect command ? w r ite protect command is to cancel any w r ite command, w h ich access to the address 00 to 7f h. w r ite protect resister can be w r itten for once. (onetime rom) once this command is executed, the dat a is protected forever . 6) w r ite protect pin (w p) ? w hen w p pin set to v cc (h level), w r ite protect is set for 256w ords (all address). w hen w p pin set to gnd (l level), it is enable to w r ite 256w ords (all address). if permanent protection is done by w r ite protect command, low e r half area (00 to 7f h address) is inhibited w r iting regardless of w p pin st ate. w p pin has a pull-dow n resister . please be lef t unconnect ed or connect to gnd w hen w p feature is not in use.
br34l02fv - w memory ics rev.a 9/24 7) acknow ledge ? acknow ledge is a sof t w a re convention used to indicate successful dat a transfers. t he t r ansmitter device w ill release the bus af ter transmitting eight bit s . (w hen inputting the slave address in the w r ite or read operation, transmitter is -com. w hen outputting the dat a in the read operation, it is this device.) ? during the ninth clock cy cle, the rece iver w ill pull the sda line low to acknow ledge that the eight bit s of dat a has been received. (w hen inputting the slave address in the w r ite or read operation, receiver is this device. w hen outputting the dat a in the read operation, it is -com.) ? t he device w ill respond w i th an acknow ledge af ter recogni tion of a st ar t condition and it s slave address (8bit). ? in the w r it e mode, the device w ill respond w i th an ack now ledge, af ter the receipt of each subsequent 8-bit w o rd (w ord address and w r ite dat a). ? in the read mode, the device w ill transmit eight bit of dat a, release the sda line, and monitor the line for an acknow ledge. ? if an acknow ledge is detected, and no st op condition is generated by the master , t he device w ill continue to transmit the dat a. if an acknow ledge is not detected, t he device w ill terminate further dat a transmissions and aw ait a st op condition before returning to the st andby mode. (see fig.1 1 acknowledge response from receiver) 18 9 scl sda sda start condition (start bit) acknowledge signal (ack signal) (from ? com) output data) ( ? com (ic output data) fig.11 acknowledge response from receiver
br34l02fv - w memory ics rev.a 10/24 z by te w r ite sda line wp s t a r t slave address 10 0 1 r / w w r i t e a c k a c k d7 data d0 s t o p fig.12 byte write cycle timing a c k word address wa 0 wa 7 a0 a1 a2 ? by using this command, the dat a is progr ammed into the indicated w o rd address. ? w hen the master generates a st op condi tion, the device begins the internal w r ite cy cle to the nonvolatile memory array . z page w r ite fig.13 page write cycle timing sda line wp slave address 10 0 1 r / w a c k a c k a c k d7 data (n) d0 data (n + 15) d0 word address (n) a c k wa 0 wa 7 a0 a1 a2 s t a r t w r i t e s t o p ? t h is device is cap able of si xteen by te page w r ite operation. ? w hen tw o or more by te dat a are inputted, the four low or der address bit s are internally incremented by one af ter the receipt of each w o rd. t he four higher order bit s of the address (w a7 to w a 4) remain const ant. ? if the master transmit s more than sixteen w o rds, prior to generating the st op condition, the address counter w ill ?roll over?, and the previous trans mitted dat a w ill be overw r itten.
br34l02fv - w memory ics rev.a 11/24 z current read sda line s t a r t slave address 11 r / w a c k a c k data s t o p 00 a2 a1 a0 d7 d0 r e a d fig.14 current read cycle timing ? in case that the previous operation is random or curr ent read (w hich includes sequential read respectively ), the internal address counter is increased by one from the last accessed address (n). t hus current read output s the dat a of the next w o rd address (n + 1). if the last command is by te or page w r ite, the inte rnal address counter st ay s at the last address (n). t hus current read output s the dat a of the w o rd address (n). ? if an acknow ledge is detected, and no st op condition is generated by the master ( -com), the device w ill continue to transmit the dat a. [ it can transmit all dat a (2kbit 256w ord) ] ? if an acknow ledge is not detected, t he device w ill terminate further dat a transmissions and aw ait a st op condition before returning to the st andby mode. not e ) if an acknow ledge is detected w i th ?low ? level, not ?high? level, command w ill bec ome sequential read. so the device transmit s the next dat a, read is not terminated. in the case of te rminating read, input acknow ledge w i th ?high? alw a y s , then input stop condition. z ra ndom re a d slave address sda line s t a r t 11 0 0 a2 a1 a0 a2 a1 a0 r / w w r i t e fig.15 random read cycle timing s t o p a c k r e a d data(n) slave address s t a r t r / w a c k 11 0 0 d7 d0 wa 0 wa 7 word address(n) a c k a c k ? random read operation allow s the master to acce ss any memory location indicated w o rd address. ? if an acknow ledge is detected, and no st op condition is generated by the master ( -com), the device w ill continue to transmit the dat a. [ it can transmit all dat a (2kbit 256w ord) ] ? if an acknow ledge is not detected, t he device w ill terminate further dat a transmissions and aw ait a st op condition before returning to the st andby mode. not e ) if an acknow ledge is detected w i th ?low ? level, not ?high? level, command w ill bec ome sequential read. so the device transmit s the next dat a, read is not terminated. in the case of te rminating read, input acknow ledge w i th ?high? alw a y s , then input stop condition.
br34l02fv - w memory ics rev.a 12/24 z se que ntia l re a d s t a r t slave address r / w a c k a c k a c k a c k r e a d data(n) data(n + x) sda line 11 00 a 2 a1 a0 d7 d7 d0 d0 s t o p fig.16 sequential read cycle timing (current read) ? if an acknow ledge is detected, and no st op condition is generated by the master ( -com), the device w ill continue to transmit the dat a. [ it can transmit all dat a (2kbit 256w ord) ] ? if an acknow ledge is not detected, t he device w ill terminate further dat a transmissions and aw ait a st op condition before returning to the st andby mode. ? t he sequential read operation can be perform ed w i th both current read and random read. not e ) if an acknow ledge is detected w i th ?low ? level, not ?high? level, command w ill bec ome sequential read. so the device transmit s the next dat a, read is not terminated. in the case of te rminating read, input acknow ledge w i th ?high? alw a y s , then input stop condition. z w r ite p r o t ect sda line wp s t a r t slave address 01 0 1 r / w w r i t e a c k a c k ? data ? s t o p fig.17 write protect cycle timing a c k word address ? ? a0 a1 a2 ? using this command, w r iting is inhibited in low e r half ar ea. (00h to 7f h address) if w r it e protect command is executed, cannot cancel the protec tion permanently . (onetime rom) ? t h is command is cancelled, if w r it e protect command is already executed. ? during this command, please be lef t w p unconnected or connect w p to gnd. ? t h is command need the period of t wr af ter stop condition just like by te or page w r ite command. during the t wr , nex t command is ignored.
br34l02fv - w memory ics rev.a 13/24 z a pplic a t ion 1) w p ef fective timing w p is fi xe d to ?h ? or ? l ? u s u a l l y . b u t i n cas e of co ntr o ll in g w p to c a nce l th e w r i t e c o mm an d, p l ease p a y att ent io n to ? w p ef fective timing ? as follow s . d u r i ng w r i t e comm a nd i n put, w r ite c o mm an d is ca nc el e d b y c o n t ro ll i ng w p ? h ? w i t h i n th e w p ca n c e l l a ti o n ef f e cti v e period. t he p e r i o d from t he st a r t co nd iti on t o th e ris i n g e d g e of t he cl oc k w h ic h t a k e i n d0 of th e d a t a (th e first b y t e of th e d a t a fo r pag e w r i t e ) i s the ca ncel la tio n in va lid pe ri od . wp in pu t i s d on? t ca re d u rin g the pe rio d . se tup ti me for ri sing edg e of the scl w h ich t a kes in d0 must be more than 100ns. t he per i od fr om th e ri si ng e d g e o f sc l w h i c h t a k e s i n d 0 to t he e n d of i n t e rn al w r i t e c y c l e (t wr ) i s th e ca nc el lat i o n ef fecti v e pe ri od . in ca se o f se ttin g w p to ?h? du ri ng t wr , w r it e o p e r a ti on is sto p p e d i n th e mi dd le a nd t he d a ta o f accessing address is not guaranteed, so t hat w r ite correct dat a again please. it is not necessary w a iting t wr (5msmax.) af ter stopping command by w p , because the device is st and by st ate. s t a r t a c k l a c k l a c k l a c k l a c k l s t o p sla ve address w ord address d ata d7 d6 d5 d4 d3 d2 d1 d0 sd a wp twr wp cancellation in v alid per iod wp cancellation eff ectiv e per iod no data will be wr itten stop of the wr ite oper ation data is not guar anteed scl sd a d 1 d 0 a ck an enlargement the r ising edge of the cloc k which tak e in d0 scl sd a d 0 a ck an enlargement the r ising edge of sd a fig.18 wp effective timing
br34l02fv - w memory ics rev.a 14/24 2) sof t w a re reset p l e a s e e x ec ut e s o f t w a r e r e s e t i n c a re t hat th e de vi ce i s a n u n e x p e c te d st at e af te r p o w e r u p a n d / or t he c o mm an d input need to be reset. t here are some kinds of sof t w a re reset. here w e show three ty pes of example as follow s . during dummy clock, please release sda bus (tied to v cc by pull up resistor). during that time, the device may pull the sda li ne low for acknow ledge or outputting or read dat a. if the ma ste r co n t ro ls the sd a li n e h i gh , i t w ill co nfli ct w i th the de vi ce ou tpu t l o w th en i t ma ke s a cu rre n t o v e r l oad . it may cause inst ant aneous pow er dow n and may damage the device. fig.19-(a) dummy clock 14 + st ar t + st ar t command command 12 1 4 13 sd a dummy clock 14 st ar t 2 scl fig.19-(b) st ar t + dummy clock 9 + st ar t command command 12 8 9 scl sd a dummy clock 9 st ar t s t a r t fig.19-(c) st ar t 9 command command 123 7 8 9 scl sd a st ar t 9 ? command st art s w i th st art condition.
br34l02fv - w memory ics rev.a 15/24 3) acknow ledge polling since the device ignore all input commands during t he internal w r ite cy cle, no ack w ill be returned. w h e n th e m a ster s e nd t he n e x t c o mm an d af ter th e w r it e c o mm an d, if th e d e v i c e r e tu rns t h e ac k, it me an s th at the program is completed. if no ack is returned, it means that the device is still busy . by using acknow ledge polling, the w a it ing time is minimized less than t wr =5 ms. i n ca se of o p e rati n g w r ite or c u rr ent r e a d ri g h t af t e r w r it e, first, s e nd t he sl av e a d d r e ss ( r /w is ? h igh? or ? l ow ? respectively ). af ter the device returns the ack, c ontinue w o rd address input or dat a output respectively . s t a r t s t a r t s t a r t s t a r t s t a r t a c k h a c k l a c k l a c k l a c k h a c k h s t o p s t o p write command sla ve address sla ve address sla ve address sla ve address w ord address d ata t wr t wr fig.20 successive write opera tion by a ckno wledge polling dur ing the inter nal wr ite cycle , no a ck will be retur ned. (a ck = high) after the inter nal wr ite cycle is completed a ck will be retur ned (a ck = lo w). then input ne xt w ord address and data. the first write command the second write command ? ? ? ? ? ? 4) command cancellation by st art and stop condition during a command input, it is canceled by the successive input s of st art condition and stop condition. (f ig.21) b u t du ri ng ac k o r data out put, th e d e v i ce ma y o u t p u t t he sda l i n e low . in su ch c a s e s, op er atio n of st art a nd st op condition is impossible, so that the reset can?t w o rk. execute the sof t w a re reset in the cases. (see page14) o per ati n g th e co mm an d c anc e l b y st art an d sto p c o nd iti on d u ri n g th e c o mm and of r a nd om re a d o r se q u e n tia l read or current read, internal addr ess counter is not confirmed. t herefore operation of cu rrent read af ter this is not valid. operate a random read in this case. fig.21 command cancella tion by st ar t and st op condition during the input of sla ve address 11 00 scl sd a st ar t condition st op condition
br34l02fv - w memory ics rev.a 16/24 5) notes for pow er supply v cc ri se s throug h the low vol t ag e regi on in w h ich in te rna l ci rcui t of ic a n d the co ntrol l e r a r e un st a b le , so tha t de vi ce may not w o rk properly due to an incomp lete reset of internal circuit. t o prevent this, the device has the feature of p .o.r. and l v cc. in the case of pow er up, keep the follow i ng c onditions to ensure functions of p .o.r. and l v cc. (1 ) it is necessary to be ?sda = ?h?? and ?scl = ?l ? or ?h?? (2 ) f o llow the recommended conditions of t r , t off , vbot for the function of p .o.r. during pow er up. t r t off vbot v cc r ising w a v e from v cc 0 recommended conditions of t r , t off , vbot belo w 10ms t r t off vbot belo w 100ms belo w 0.3v belo w 0.2v abo v e 10ms abo v e 10ms (3 ) prevent sda and scl from being ?hi-z ? . in case that condition 1. and/or 2. cannot be met, t a ke follow i ng actions. a) unable to keep condition 1.(sda is ?low ? during pow er up.) control sda, scl to be ?high? as figure below . t lo w t dh t su:d a t after v cc becomes stab le sd a scl v cc a) scl = "h" and sd a = "l" t su:d a t after v cc becomes stab le b) scl = "l" and sd a = "l" b) unable to keep condition 2. af ter pow er becomes st able, execute sof t w a re reset. (see page14) c) unable to keep both conditions 1 and 2. f o llow the instruction a fi rst, then the instruction b. ? l v cc circuit l v cc circuit inhibit w r ite operation at low volt age, and prevent an inadvertent w r ite. below the l v cc volt age (t y p . = 1.2v), w r ite operati on is inhibited.
br34l02fv - w memory ics rev.a 17/24 6) i/o circuit ? pull up resister of sda pin t he pull up resister is needed because sda is nmos open drain. decide the value of this resister (r pu ) properly , by considering v il , i l characteristics of a controlle r w h ich control the device and v oh , i ol characteristics of the device. if large r pu is chosen, clock frequency need to be slow . in case of small r pu , the operating current increases. ? max i mum of r pu max i mum of r pu is determined by follow i ng factor . c sda rise time determined by r pu and the cap a cit ance of bus line (cbus) must be less than t r . and the other timing must keep the conditions of ac spec. d w hen sda bus is high, the volt age a of sda bus determined by a tot a l input leak (i l ) of the all devices connected to the bus and r pu must be enough higher than input high le vel of a controller and the device, including noise margin 0.2v cc . a il il micro computer br24lxx sda pin r pu the capacitance of bus line (cbus) v cc ? i l r pu ? 0.2v cc v ih r pu 0.8v cc ? v ih il r pu 0.8 3 ? 0.7 3 10 10 ? 6 300 [k ? ] examples : when v cc = 3v i l = 10 a v ih = 0.7v cc according to 2
br34l02fv - w memory ics rev.a 18/24 ? t he minimum value r pu t he minimum value of r pu is determined by follow i ng factors. c meet the condition that v olmax = 0.4v , i olmax = 3ma w hen the device out put low on sda line. r pu v cc ? v ol i ol i ol v cc ? v ol r pu d v olmax ( = 0.4v) must be low e r than the input low leve l of the controller and the eeprom including recommended noise margin (0.1v cc ). v olmax v il ? 0.1v cc r pu 3 ? 0.4 3 10 ? 3 867 [ ? ] examples : v cc = 3v, v ol = 0.4v, i ol = 3ma, the v il of the controller and the eeprom is v il = 0.3v cc according to and so that condition is met 1 2 v ol v il = 0.4[v] = 0.3 3 = 0.9[v] ? pull up resister of scl pin in the case that scl is controlled by cmos output, the pull up resist er of scl is not needed. but in the case that there is a timi ng at w h ich scl is hi-z , connect scl to v cc w i th pull up resister . several several dozen k ? is recommended as a pull up resister , w h ich is considered w i th the driving ability of the output port of the controller . 7) connections of a0, a1, a2, w p pin ? connections of device address pin (a0, a1, a2) t he st ate of device address pin are comp ared w i th the device address send by the master , then one of the devices w h ich are connected to the identical bus is select ed. pull up or dow n these pins, or connect them to v cc or gnd. ? connections of w p pin t he w p input allow s or inhibit s w r ite operations. w hen w p is high, only read is available and w r it e to any address is inhibited. both read and w r ite are available w hen w p is low . in the case that the device is used as a rom, it is recommended that w p is pulled up or connected to v cc . in the case that both read and w r it e are operated, w p pin must be pulled dow n or connected to gnd, controlled, or be lef t unconnected. (w p has a pull dow n resister . so it is allow ed to be lef t unconnect)
br34l02fv - w memory ics rev.a 19/24 8) notes for noise on v cc ? about by p a ss cap a citor noise and surges on pow er line may cause the abnormal f unction. it is recommended that the by p a ss cap a citors (0.1 f ) are att a ched on the v cc and gnd line beside the device. t he att a chment of by p a ss cap a citors on t he board near by connector is also recommended. gnd v cc print base ic capacitor 0.01 to 0.1 f capacitor 10 to 100 f 9) t he notice about the connection of controller ? about r s t he open drain interface is recommended for sda port in i 2 c bus. but, in the case that t r i-st ate cmos interface is applied to sda, insert a series resister r s betw een sda pin of the dev ice and a pull up resister r pu . it limit s the current from pmos of controller to nmos of eeprom. r s also protect s sda pin from surges. t herefore, r s is able to be used though sda port is open drain. sda pin r pu r s controller eeprom "h" output of controller "l" output of eeprom ack scl sda the "h" output of controller and the "l" output of eeprom may cause current overload to sda line.
br34l02fv - w memory ics rev.a 20/24 ? t he maximum value of r s t he maximum value of r s is determined by follow i ng factors. c sda rise time determined by r pu and the cap a cit ance of bus line (c bus) of sda must be less than t r . and the other timing must also keep t he conditions of the ac timing. d w hen the device output s low on sda line, t he volt age of the bus a determined by r pu and r s must be low e r than the input s low level of the cont roller , including recommended noise margin (0.1v cc ). v ol v il r pu v cc r s controller eeprom a capacitance of bus line (cbus) r s r pu v il ? v ol ? 0.1v cc 1.1v cc ? i il r s 20 10 3 0.3 3 ? 0.4 ? 0.1 3 1.1 3 ? 0.3 3 + v ol + 0.1v cc i ol (v cc ? v ol ) r s r pu + r s 1.67 [k ? ] examples : when v cc = 3v, v il = 0.3v cc , v ol = 0.4v, r pu = 20k ? according to 2 ? t he minimum value of rs t he minimum value of r s is determined by the current over load due to the conflict on the bus. t he current overload may cause noises on the pow er line and inst ant aneous pow er dow n. t he follow i ng conditions must be met, w here is the max i mum permissible current. t he maximum permissible current depends on v cc line impedance and so on. it need to be less than 10ma for eeprom. r s v cc r s 3 10 10 ? 3 v cc r s 300 [ ? ] examples : when v cc = 3v, = 10ma r pu r s controller eeprom "l" output "h" output maximum current
br34l02fv - w memory ics rev.a 21/24 10) t he special character dat a t he follow i ng characteristic dat a are ty p value. 2 6 5 4 3 2 1 0 01 34 5 h input voltage : v ih (v) 6 fig.22 high input voltage v ih (a0,a1,a2,scl,sda,wp) supply voltage : v cc (v) spec ta = 85 c ta = 25 c ta =? 40 c 2 6 5 4 3 2 1 0 01 34 5 l input voltage : v il (v) 6 fig.23 low input voltage v il (a0,a1,a2,scl,sda,wp) supply voltage : v cc (v) spec ta = 85 c ta = 25 c ta =? 40 c 2 1 0.8 0.6 0.4 0.2 0 01 34 5 l output voltage : v ol (v) 6 fig.24 low output voltage v ol ? i ol (v cc = 1.8v) l output current : i ol (ma) spec ta = 85 c ta = 25 c ta =? 40 c 2 1 0.8 0.6 0.4 0.2 0 01 34 5 l output voltage : v ol (v) 6 fig.25 low output voltage v ol ? i ol (v cc = 2.5v) l output current : i ol (ma) spec ta = 85 c ta = 25 c ta =? 40 c 2 1.2 1 0.8 0.6 0.4 0.2 0 01 34 5 input leak current : i li ( a) 6 fig.26 input leakage current i li (a0,a1,a2,scl,wp) supply voltage : v cc (v) spec ta = 85 c ta = 25 c ta =? 40 c 2 16 12 8 4 0 01 34 5 input leak current : i li ( a) 6 fig.27 input leakage current i li (wp) supply voltage : v cc (v) spec ta = 85 c ta = 25 c ta =? 40 c 2 1.2 1 0.8 0.6 0.4 0.2 0 01 34 6 5 output leak current : i lo ( a) 2 2.5 2 1.5 1 0.5 0 01 34 6 5 current consumption at writing : i cc 1 (ma) 2 0.6 0.5 0.4 0.3 0.2 0.1 0 01 34 5 current consumption at reading : i cc 2 (ma) 6 fig.30 read operating current i cc 2 (f scl = 400khz) supply voltage : v cc (v) spec ta = 85 c ta = 25 c ta =? 40 c f scl =400khz data=aah fig.29 write operating current i cc 1 (f scl = 400khz) supply voltage : v cc (v) spec ta = 85 c ta = 25 c ta =? 40 c f scl = 400khz data = aah fig.28 output leakage current i lo (sda) supply voltage : v cc (v) spec ta = 85 c ta = 25 c ta =? 40 c
br34l02fv - w memory ics rev.a 22/24 2 2.5 2 1.5 1 0.5 0 01 34 6 5 current consumption at writing : i cc 1 (ma) 2 0.6 0.5 0.4 0.3 0.2 0.1 0 01 34 6 5 current consumption at reading : i cc 2 (ma) 2 2.5 2 1.5 1 0.5 0 01 34 5 standby current : i sb ( a) 6 fig.33 standby current i sb supply voltage : v cc (v) spec ta = 85 c ta = 25 c ta =? 40 c fig.31 write operating current i cc 1 (f scl = 100khz) supply voltage : v cc (v) spec ta = 85 c ta = 25 c ta =? 40 c f scl = 100khz data = aah fig.32 read operating current i cc 2 (f scl = 100khz) supply voltage : v cc (v) spec ta = 85 c ta = 25 c ta =? 40 c f scl = 100khz data = aah 2 10000 1000 100 10 1 01 34 5 scl frequency : f scl (khz) 6 fig.34 clock frequency f scl supply voltage : v cc (v) spec1 spec2 ta = 85 c ta = 25 c ta =? 40 c spec1 : fast-mode spec2 : standard-mode 2 5 3 4 2 1 0 01 34 5 data clk h time : t high ( s) 6 fig.35 data clock "h" period t high supply voltage : v cc (v) spec1 spec2 ta = 85 c ta = 25 c ta =? 40 c spec1 : fast-mode spec2 : standard-mode 2 5 3 4 2 1 0 01 34 5 data clk l time : t low ( s) 6 fig.36 data clock "l" period t low supply voltage : v cc (v) spec1 spec2 ta = 85 c ta = 25 c ta =? 40 c spec1 : fast-mode spec2 : standard-mode 2 5 3 4 2 1 0 01 34 5 start condition hold time : t hd:sta ( s) 6 fig.37 start condition hold time t hd:sta supply voltage : v cc (v) spec1 spec2 ta = 85 c ta = 25 c ta =? 40 c spec1 : fast-mode spec2 : standard-mode 2 6 3 4 5 2 1 0 01 34 5 start condition set up time : t su:sta ( s) 6 fig.38 start condition setup time t su:sta supply voltage : v cc (v) spec1 spec2 ta = 85 c ta = 25 c ta =? 40 c spec1 : fast-mode spec2 : standard-mode 2 50 ? 50 0 ? 100 ? 150 ? 200 01 34 5 input data hold time : t hd:dat (ns) 6 fig.39 input data hold time t hd:dat (high) supply voltage : v cc (v) spec1,2 ta = 85 c ta = 25 c ta =? 40 c spec1 : fast-mode spec2 : standard-mode
br34l02fv - w memory ics rev.a 23/24 2 50 ? 50 0 ? 100 ? 150 ? 200 01 34 5 input data hold time : t hd:dat (ns) 6 fig.40 input data hold time t hd:dat (low) supply voltage : v cc (v) spec1,2 ta = 85 c ta = 25 c ta =? 40 c spec1 : fast-mode spec2 : standard-mode 2 300 100 200 0 ? 100 ? 200 01 34 5 input data set up time : t su:dat (ns) 6 fig.41 input data setup time t su:dat (high) supply voltage : v cc (v) spec2 spec1 ta = 85 c ta = 25 c ta =? 40 c spec1 : fast-mode spec2 : standard-mode 2 300 100 200 0 ? 100 ? 200 01 34 5 input data set up time : t su:dat (ns) 6 fig.42 input data setup time t su:dat (low) supply voltage : v cc (v) spec2 spec1 ta = 85 c ta = 25 c ta =? 40 c spec1 : fast-mode spec2 : standard-mode 2 4 2 3 1 0 01 34 5 output data delay time : t pd ( s) 6 fig.43 output data delay time t pd 0 supply voltage : v cc (v) spec2 spec2 spec1 spec1 ta = 85 c ta = 25 c ta =? 40 c spec1 : fast-mode spec2 : standard-mode 2 4 2 3 1 0 01 34 5 output data delay time : t pd ( s) 6 fig.44 output data delay time t pd 1 supply voltage : v cc (v) spec2 spec2 spec1 spec1 ta = 85 c ta = 25 c ta =? 40 c spec1 : fast-mode spec2 : standard-mode 2 4 2 3 1 0 01 34 5 output data hold time : t dh ( s) 6 fig.45 output data hold time t dh 0 supply voltage : v cc (v) spec2 spec2 spec1 spec1 ta = 85 c ta = 25 c ta =? 40 c spec1 : fast-mode spec2 : standard-mode 2 4 2 3 1 0 01 34 6 2 5 3 4 2 1 0 01 34 6 2 5 3 4 2 1 0 01 34 5 bus open time before transmission : t buf ( s) 6 fig.48 bus free time t buf supply voltage : v cc (v) spec1 spec2 ta = 85 c ta = 25 c ta =? 40 c spec1 : fast-mode spec2 : standard-mode 5 stop condition set up time : t su:sto ( s) fig.47 stop condition setup time t su:sto supply voltage : v cc (v) spec1 spec2 ta = 85 c ta = 25 c ta =? 40 c spec1 : fast-mode spec2 : standard-mode 5 output data hold time : t dh ( s) fig.46 output data hold time t dh 1 supply voltage : v cc (v) spec2 spec2 spec1 spec1 ta = 85 c ta = 25 c ta =? 40 c spec1 : fast-mode spec2 : standard-mode
br34l02fv - w memory ics rev.a 24/24 2 6 3 4 5 2 1 0 01 34 6 2 0.6 0.3 0.4 0.5 0.2 0.1 0 01 34 6 2 0.6 0.3 0.4 0.5 0.2 0.1 0 01 34 5 noise reduction effective time : t i (scl l) ( s) 6 fig.51 noise spike width t i (scl l) supply voltage : v cc (v) spec1,2 ta = 85 c ta = 25 c ta =? 40 c spec1 : fast-mode spec2 : standard-mode 5 internal write cycle time : t wr (ms) fig.49 write cycle time t wr supply voltage : v cc (v) spec1,2 ta = 85 c ta = 25 c ta =? 40 c spec1 : fast-mode spec2 : standard-mode 5 noise reduction effective time : t i (scl h) ( s) fig.50 noise spike width t i (scl h) supply voltage : v cc (v) spec1,2 ta = 85 c ta = 25 c ta =? 40 c spec1 : fast-mode spec2 : standard-mode 2 0.6 0.3 0.4 0.5 0.2 0.1 0 01 34 6 2 0.6 0.3 0.4 0.5 0.2 0.1 0 01 34 6 2 0.2 ? 0.4 ? 0.2 0 ? 0.6 01 34 5 wp set up time : t su:wp ( s) 6 fig.54 wp setup time t su:wp supply voltage : v cc (v) spec1,2 ta = 85 c ta = 25 c ta =? 40 c spec1 : fast-mode spec2 : standard-mode 5 noise reduction effective time : t i (sda h) ( s) fig.52 noise spike width t i (sda h) supply voltage : v cc (v) spec1,2 ta = 85 c ta = 25 c ta =? 40 c spec1 : fast-mode spec2 : standard-mode 5 noise reduction effective time : t i (sda l) ( s) fig.53 noise spike width t i (sda l) supply voltage : v cc (v) spec1,2 ta = 85 c ta = 25 c ta =? 40 c spec1 : fast-mode spec2 : standard-mode 2 1.2 0.6 0.8 1 0.4 0.2 0 01 34 5 wp effective time : t high:wp ( s) 6 fig.55 wp high period t high:wp supply voltage : v cc (v) spec1,2 ta = 85 c ta = 25 c ta =? 40 c spec1 : fast-mode spec2 : standard-mode
appendix appendix1-rev1.1 the products listed in this document are designed to be used with ordinary electronic equipment or devices (such as audio visual equipment, office-automation equipment, communications devices, electrical appliances and electronic toys). should you intend to use these products with equipment or devices which require an extremely high level of reliability and the malfunction of with would directly endanger human life (such as medical instruments, transportation equipment, aerospace machinery, nuclear-reactor controllers, fuel controllers and other safety devices), please be sure to consult with our sales representative in advance. notes no technical content pages of this document may be reproduced in any form or transmitted by any means without prior permission of rohm co.,ltd. the contents described herein are subject to change without notice. the specifications for the product described in this document are for reference only. upon actual use, therefore, please request that specifications to be separately delivered. application circuit diagrams and circuit constants contained herein are shown as examples of standard use and operation. please pay careful attention to the peripheral conditions when designing circuits and deciding upon circuit constants in the set. any data, including, but not limited to application circuit diagrams information, described herein are intended only as illustrations of such devices and not as the specifications for such devices. rohm co.,ltd. disclaims any warranty that any use of such devices shall be free from infringement of any third party's intellectual property rights or other proprietary rights, and further, assumes no liability of whatsoever nature in the event of any such infringement, or arising from or connected with or related to the use of such devices. upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or otherwise dispose of the same, no express or implied right or license to practice or commercially exploit any intellectual property rights or other proprietary rights owned or controlled by rohm co., ltd. is granted to any such buyer. products listed in this document are no antiradiation design. about export control order in japan products described herein are the objects of controlled goods in annex 1 (item 16) of export trade control order in japan. in case of export from japan, please confirm if it applies to "objective" criteria or an "informed" (by miti clause) on the basis of "catch all controls for non-proliferation of weapons of mass destruction.

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